The present invention is generally directed to a system and method for the precisely controlled tuning of oscillation frequency generated for use in various electronic applications. More specifically, the present invention is directed to a system and method for optimizing the incremental adjustability of oscillation frequency in systems that employ inductive-capacitive (L-C) resonance circuits to generate the oscillation. The subject system and method provide for down-converting the actual capacitance contributed by the capacitor portions of such resonance circuits, to reduce the incremental change in capacitance they may realize, and thereby augment their capacitive tuning resolution.
Advances in the electronics industry continue to yield smaller device geometries and higher speeds of circuit operation. As a result, demand continues to rise for ever more precise control of frequency references generated during phase locked loop and other such timing-sensitive applications. Oscillation circuits, such as Voltage Controlled Oscillators (VCO), have traditionally found use in many applications. More recently, Digital Phase-locked loops (DPLL's) employing Digitally Controlled Oscillators (DCO's) are becoming more prevalent in various applications to provide digitally programmable frequency references. While the digital control makes for precise selection from available frequency levels, the incremental steps between frequency levels presents certain challenges. The incremental step size must be sufficiently fine, for instance, to meet jitter requirements in most cases. That is, the frequency must be adjustable with sufficiently fine resolution to meet applicable performance requirements. The required fineness is normally not attainable simply by appropriate selection of device attributes. The requisite attributes are often beyond the physical limits of known fabrication processes for devices.
For example, in digital oscillation systems employing so-called tank, or inductive-capacitance resonant, circuits (L-C DCO), frequency may be tuned by selectively varying the tank capacitance in small incremental steps. But the capacitance step size required in many cases is well below the minimum capacitance size of any capacitor device that may actually be realized physically with device fabrication processes heretofore known in the art. Consequently, various measures have been taken in the art to nonetheless attain the desired degree of tuning resolution, though each is not without notable drawbacks and practical limitations.
Examples of such measures are disclosed in the following publications: Fanori et al., “Capacitive Degeneration in LC-Tank Oscillator for DCO Fine-Frequency Tuning,” IEEE Journal of Solid-State Circuits, vol. 45, no. 12 (December 2010); Vercesi et al., “A Dither-Less All Digital PLL for Cellular Transmitters,” IEEE Journal of Solid-State Circuits, vol. 47, no. 8 (August 2012); Chen et al., “A 9 GHz Dual-Mode Digitally Controlled Oscillator for GSM UMTS Transceivers in 65 nm CMOS,” IEEE Asian Solid-State Circuits Conference (November 2007); and Yao et al., “A 2.8-3.2-GHz Fractional-N Digital PLL with ADC-assisted TDC and Inductively Coupled Fine-Tuning DCO,” IEEE Journal of Solid-State Circuits, vol. 47, no. 3 (March 2013).
In one approach, high-speed dithering is employed to get around this physical limitation in capacitor size. Techniques such as Delta-Sigma Modulator (DSM) dithering are used to reduce the effective DCO step size enough to keep the quantization noise to levels below an analog DCO noise floor. Because they generally involve adding uncorrelated noise to a given input signal in order to average out noise levels, these dithering techniques may provide an undue source of charge injection phase noise, especially if not properly re-timed with a DCO clock mechanism.
Other approaches known in the art seek to avoid this problem by incorporating various techniques to effectively reduce the switched capacitors used in fine tuning the adjustment step size. In one such approach, a differential, cross-coupled pair of MOSFET transistors disposed between course and fine tuning capacitors of an L-C tank circuit is capacitively degenerated to “shrink” the effective tank capacitance as a function of the pair's MOS transconductance gm. The differential pair is essentially diminished in quality factor (based on gm and the equivalent capacitance at the tank) to yield a reduction in the equivalent tank capacitance. While capacitance shrink factors on the order of 250 may be achieved in this manner under certain conditions, capacitor size must be set dependent upon MOS transconductance gm which fluctuates with process and temperature. Moreover, multiple capacitance “legs” of the tank circuit must be used to optimally control current to differential pair's capacitive degeneration “leg.”
In another approach, relatively small capacitors are added in series with a fine tuning capacitor (varactor) array of an L-C tank circuit to form a capacitive divider. This serves to scale down the capacitance of each unit cell of the varactor array is switched during operation. Under certain conditions, frequency step sizes on the order of 1.5 kHz for a 2 GHz carrier frequency output have been realized, corresponding effectively to an incremental capacitance step of 23 aF in 65 nm CMOS technology. Still, the considerable drawbacks of this approach include its undue sensitivity to parasitic capacitances which leads to excessive variation between designed and actually realized step sizes. The inclusion of multiple metal capacitors positioned about a varactor array leads to inefficient consumption of precious chip area. The minimum realizable capacitance of metal capacitors also tends to be relatively large in size; hence, their use inherently limits the range of realizable step sizes.
In yet another approach, a one-turn coupling loop is disposed within a two-turn spiral on-chip inductor of an L-C tank circuit. The coupling loop is isolated from the inductor to form a transformer therewith. A pair of cross-coupled CMOS transistors and a level-2 course tuning capacitor bank are connected to the inductor, while a level-1 course tuning capacitor bank and a fine tuning capacitor bank are separately connected to the coupling loop. The capacitance applied to the coupling loop is found to be reduced by a factor of 16.6 when translated to the inductor, yielding a 20 kHz frequency step size for a 3.2 GHz carrier frequency output under certain conditions.
This approach transforms the high-swing waveforms appearing at the tank circuit's output nodes to low-swing waveforms for varactors employed in the level-1 course tuning capacitor bank and a fine tuning capacitor banks connected to the coupling loop. This improves the apparent linearity of the varactors at the coupling loop. Nonetheless, the inductor's quality factor Q is degraded by the coupling loop. To keep Q degradation within tolerable limits, the coupling loop's capacitive loading must be limited accordingly. Limiting the quality factor degradation to at most 3.5% under certain conditions, for example, requires the capacitive load at the coupling loop to be kept less than 3 pF. There is also the theoretical potential for multiple peaks in the coupling loop's frequency response, as a high-order system may be formed by virtue of the coupling loop's stronger coupling to the inner turn of the inductor than to the outer turn.
There is therefore a need for a system and method which accurately and reliably provide ample fineness in frequency tuning resolution, without the many drawbacks plaguing these and other approaches heretofore known in the art. There is a need for a system and method which provide a reduction in the incremental step size by which capacitance may be adjusted toward that end in an L-C oscillation circuit, and beyond the physical limits imposed on individual devices by their fabrication processes.